1. Field of the Invention
The present invention relates to a high-speed integrated circuit device and a method for manufacturing the same.
2. Description of the Related Art
Semiconductor integrated circuits have recently been making great progress in areas of operation speed and power consumption. Since their applications are wide and many, MOS semiconductor integrated circuits, especially BiCMOS semiconductor integrated circuits, are becoming increasingly important. Given this growing importance, a number of developments have occurred. For example, CMOS devices are miniaturized and their power supply voltage have decreased, bipolar transistors are also miniaturized and their parasitic resistance and parasitic capacitance are reduced by using a self-alignment technique, and many transistors have changed from conventional BJT (Bipolar Junction Transistors) using homojunction to HBT (Hetero Bipolar Transistors) using heterojunction. Furthermore, the gate electrode of a MOSFET (referred to as a MOS transistor) and the external base electrode of a bipolar transistor in a conventional CMOS (Complementary MOS) integrated circuit are formed of polysilicon. However, when an HBT having SiGe in its base electrode is used as a bipolar transistor, a low-temperature manufacturing process is required in order to prevent a hetero-epitaxial growing layer from being deformed. If polysilicon requiring a high-temperature manufacturing process is applied to a gate electrode of a MOS transistor or an external base electrode of a bipolar transistor, the degrees of freedom in the process is restricted and the process becomes complicated.
FIGS. 1 to 3 show an example of a manufacturing process for manufacturing a semiconductor integrated circuit device in which polysilicon is used for a gate electrode. This device comprises a P-type silicon (100) semiconductor substrate 1. A P-type epitaxial growing layer 5 is formed on the semiconductor substrate 1. An element isolating region having a deep trench-type element isolation insulating film 2 and a shallow trench-type element isolation insulating film 3 are each formed in respective regions of the semiconductor substrate 1, where a PMOS transistor and a bipolar transistor are formed, and where an NMOS transistor and a bipolar transistor are formed. These films 2 and 3 are constituted by, for example, a silicon oxide film, and polysilicon can often be buried into the deep film 2. The P-type epitaxial growing layers 5 corresponding to the regions (PMOS and bipolar forming regions) where the PMOS and bipolar transistors are formed, are N-type well regions, under which N.sup.+ -type burying regions 4 are formed. One of the burying regions 4, which corresponds to the bipolar forming region, is connected to an N.sup.+ -type diffusion region 6 which is exposed to the surface of the semiconductor substrate 1 and serves as a collector. P.sup.+ -type source and drain regions 7 are formed in the PMOS forming region, and a polysilicon gate electrode 8 is formed above a region between the source and drain regions 7. A sidewall insulating film 9 such as a silicon oxide film is formed on the gate electrode 8, and a gate insulating film 12 is formed by thermal oxidation between the gate electrode 8 and the semiconductor substrate 1.
In the region (NMOS forming region) where the NMOS transistor is formed, N.sup.+ -type source and drain regions 10 are formed. Further, a gate oxide film 12 is formed on a region between the source and drain regions 10, and a polysilicon gate electrode 8 having a sidewall insulating film 9 is formed on the gate oxide film 12. The gate electrode 8 is doped with impurities and heated at about 900.degree. to 1000.degree. C. to activate these impurities. P.sup.- -type impurity diffusion regions 11 are formed in contact with the P.sup.+ -type source and drain regions 7, while N.sup.- -type impurity diffusion regions 13 are formed in contact with the N.sup.+ -type source and drain regions 10. Both the regions 11 and 13 have an LDD structure (FIG. 1).
Subsequently, the surfaces of the NMOS and PMOS forming regions are coated with an insulating film 14 such as a silicon oxide film, and the bipolar transistor is formed in the bipolar forming region. A P-type internal base region 18 of single crystal SiGe, which is epitaxially grown and has a thickness of about 50 to 200 nm, is formed in a predetermined area of the bipolar forming region. The composition ratio of Ge to Si in the SiGe epitaxial growing layer of the internal base region 18 is arbitrary and can be represented as Si.sub.1-x Ge.sub.x. Taking into account of the matching of lattice of SiGe with the P-type silicon epitaxial growing layer 5 on which the SiGe epitaxial growing layer is formed would suggest that the value of x be set equal to about 0.1 to 0.2.
An insulating film 16 such as a silicon oxide film, and then a polysilicon film 17 are formed on the P-type internal base region 18 serving as an external base leading electrode. An opening is formed in an emitter forming region of the polysilicon film 17. After that, the surface of the bipolar forming region including the polysilicon film 17 and the like is coated with an insulating film 15 (FIG. 2). The insulating film 16 is then etched to form an opening of an emitter region. This opening and the surface of the insulating film 15 are doped with N-type impurities to form a polysilicon layer 21. Subsequently, the N-type impurities are diffused by RTA to form the emitter region in the P-type internal base region 18, and the polysilicon layer 21 then serves as an emitter electrode. Next, an insulating film 20 such as a silicon oxide film is formed so as to cover the surface of the emitter electrode 21, and necessary contact holes are formed in the emitter, base, and collector regions of the bipolar transistor. A wiring collector electrode C formed of, e.g., aluminum is connected to the N.sup.+ -type diffusion region 6, a wiring base electrode B is connected to the external base leading electrode 17, and a wiring emitter electrode E is connected to the emitter electrode 21. Finally, metal wiring electrodes 19 formed of, e.g., aluminum are connected to the source and drain regions 7 and 10 of the respective NMOS and PMOS forming regions (FIG. 3).